1. Field of the Invention
The present invention relates to a phase-change random access memory device and a semiconductor memory device including a memory cell structure in which phase-change elements and diodes are connected in series.
Priority is claimed on Japanese Patent Application No. 2007-214521, filed Aug. 21, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
A phase-change random access memory (PRAM) device is attracting attention as a nonvolatile memory capable of high-speed writing. However, a PRAM device has a disadvantage of requiring comparatively high current when writing to the memory cell. When memory cell is selected by using a metal oxide semiconductor (MOS) transistor which requires large write current, the layout size of the switching MOS transistor increases in order to secure write current while the size of the phase-change elements constituting the memory cell can be reduced. To secure write current with a small cell size, a memory cell structure called “diode matrix ROM” is proposed, in which phase-change elements and diodes are connected in series.
FIG. 7 is a memory cell structure of a diode matrix ROM. FIG. 8 is a cross-sectional view of the memory cell structure shown in FIG. 7. FIG. 9 is an equivalent circuit of the memory cell structure shown in FIG. 7.
As shown in FIGS. 7, 8, and 9, in this memory cell structure, a pn junction diode 203 is formed on a diffusion layer 202 embedded in a silicon (Si) substrate 201. A bottom electrode 206 is formed on the diode 203 with a contact 204 and a mid-contact 205 in between. A phase-change film (GST {GeSbTe} film) 207 is formed on the bottom electrode 206. A top electrode 208 is formed on the phase-change film 207. Forming the bottom electrode 206, the phase-change film 207, and the top electrode 208 in this manner obtains a phase-change element 209 that is connected in series to the diode 203. A memory cell MC is constituted by connecting the phase-change element 209 in series with the diode 203. A memory cell MC is arranged at each point of intersection between a diffusion layer 202 forming a word line WL and a top electrode 208 forming a bit line BL. The bottom electrode 206 is formed as a heat plug (a section which heats by current-concentration) for generating phase-change. In this memory cell structure, write current is reduced by providing an insulating film (side wall) 210 inside the opening where the bottom electrode 206 is arranged, making the heater smaller than the opening diameter.
Such a diode matrix ROM memory cell structure is known as a cross-point cell structure, and can realize a minimum cell area, specifically a cell size of 4F2 (where F is a minimum feature size of a process).
With this memory cell structure, one effect of reducing the cell size is that write current concentrates in the word line (ground line) WL. When memory cells (bits) on a same word line are selected, current for simultaneous writing concentrates in the word line WL. As a result, the resistance of the word line WL causes its potential to increase, whereby the write current of each bit decreases.
For example, in FIG. 9, two memory cells on the same word line WL are in write status. Here, among the plurality of bit lines BL along the vertical direction, the selected bit lines BL are indicated by H (thick solid line) and the unselected bit lines BL are indicated by L (thin solid line). Among the word lines WL along the horizontal direction, the selected word line WL is indicated by L (thick solid line), and the unselected word lines WL are indicated by H (thin solid line). As indicated by the broken line in FIG. 9, write current flows from the two selected bit lines BL and through the memory cells MC to the selected word line WL. Therefore in this case, write current from two memory cells MC concentrates in one word line WL. Therefore, twice the current required for writing each memory cell MC flows to one word line WL.
Since a phase-change random access memory device generally requires a large write current of approximately 500 μA to several mA, when current concentrates in a word line WL, the potential of the word line WL increases greatly. When performing reading, this concentration of current in the word line WL leads to a rise in the potential of the word line WL, which adversely affects the data sensing operation. A phase-change random access memory device has a comparatively long writing time (approximately several ten ns to several hundred ns). Therefore, when the phase-change random access memory device is used as a memory cell MC for applications with a short read/write cycle such as a DRAM, there is a possibility of mixture of read/write operations. Specifically, it is conceivable that, a read of one memory cell MC is performed on a word line WL, while a write of a different memory cell MC on the same word line WL is performed. In this case, since a large current is required for writing, concentration of this write current makes the potential of the word line WL increase. Consequently, the required voltage is not applied to the phase-change element 209 of a different memory cell MC on the same word line WL and the current for reading decreases, making reading impossible or reducing the read speed.
Currently there is a demand for semiconductor memories to perform multi-bit and high-speed reading and writing. There is a consequent trend toward increasing the number of bits to which reading/writing is performed simultaneously. As the number of bits increases, more bits are activated within same mats (regions having common ground lines), which generates more current concentration.
Accordingly, to prevent such concentration of write current in word lines WL, United States Patent Application, Publication No. 2005-270883 and ‘Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)’, VLSI Symposium 2007 disclose a configuration for arranging a MOS transistor below a memory cell MC. Specifically, in this configuration, two, four, or eight memory cells MC are connected in a single MOS transistor. Since the current travels in the direction of the bit lines BL instead of the word lines WL, concentration of current can be avoided.
However, when the MOS transistor is arranged below the memory cells MC in this manner, limitation regarding the layout of the MOS transistor results in a cell size of 6F2. This results in a problem that the cell is larger than the 4F2 case above.